Method for forming pattern of stacked film

ABSTRACT

A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF 4  and O 2  is used, and suitably, a gas ratio of CF 4  and O 2  in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for forming a patternof a stacked film, and more particularly, to a method for forming astacked film composed of a polysilicon film and an upper oxide film,which are formed on a lower oxide film.

[0003] 2. Description of the Related Art

[0004]FIGS. 1A and 1B and FIGS. 2A and 2B illustrate schematic views oftwo-layer structures, each of which is composed of a polysilicon filmand an upper oxide film for fabricating a conventional thin filmtransistor. FIG. 1A is a plan view of a two-layer structure, and FIG. 1Bis a cross-sectional view obtained by cutting the two-layer structure ofFIG. 1A along the line I-I. FIG. 2A is a plan view of a two-layerstructure, and FIG. 2B is a cross-sectional view obtained by cutting thetwo-layer structure of FIG. 2A along the line II-II.

[0005] In each case, the lower oxide film (SiO₂) 502 is deposited on theglass substrate 501 with a thickness of approximately 300 nm. Next, thesilicon film 503 and the upper oxide film 504, which configure thetwo-layer structure, are deposited on the lower oxide film 502 withthicknesses of 60 m and 10 nm, respectively. Subsequently, the siliconfilm 503 is crystallized by an excimer laser, thus forming a polysilicon(poly-Si) film.

[0006] Next, dry etching is conducted simultaneously for the siliconfilm 503 and the upper oxide film 504, which configure the two-layerstructure, followed by formation of the side face of the two-layerstructure of the polysilicon film 503 with the thickness of 60 nm andupper oxide film 504 with the thickness of 10 nm at an angle ofapproximately 90° (vertical shape) with respect to the glass substrate.

[0007] The reason that the two-layer structure is composed of thepolysilicon film and the upper oxide film is to protect the surface ofthe polysilicon film, which is an active layer, and keep the samesurface clean. In addition, the reason that the film thicknesses in thetwo-layer structure are set at 10 nm for the upper oxide film and 60 nmfor the polysilicon film is for thinning the film thickness of the upperoxide film as much as possible and facilitating the formation of thetwo-layer structure by dry etching. Detailed contents of this will bedescribed later in a section of a method for forming a two-layerstructure.

[0008] After the formation of the two-layer structure described above,high-concentration phosphorus ions are doped into the polysilicon filmin the two-layer structure, thus forming a source/drain (not shown).Subsequently, low-concentration phosphorus ions are doped, thus forminga lightly doped drain (LDD). Thereafter, the gate oxide film 505 isformed in a thickness of 45 nm, followed by deposition of a two-layerfilm formed of a micro-crystalline silicon (μc-Si) film 506 and the Crfilm 507. Then, the two-layer film is etched, thus forming the gateelectrode 521. As the gate electrode 521, the Cr film 507 made of ametal with a high melting point is used because of its outstandingability to resist heat, as well as its low electric resistance.Moreover, the μc-Si film 506, which has a specific work function, isused as an interlayer film because of its easiness in controllingthreshold values. For the high melting point metal utilized as a gatematerial, W, Mo, Ti, Ta or a silicide film of any of these can be usedas well as Cr. Thereafter, a heat treatment at a temperature of 350° C.or more is conducted, thus activating impurities contained in thepolysilicon film of the two-layer structure, into which the phosphorusis doped. Thus, the electric resistance of the polysilicon in theportion into which the phosphorus is doped is lowered.

[0009] After the steps described above, a protective oxide film (notshown) is further deposited in a thickness of 300 nm. Then, a contact tocommunicate with the polysilicon film in the activated two-layerstructure is opened in the protective oxide film and the gate oxidefilm, and Al wiring is formed thereon. Thus, a desired thin filmtransistor is obtained.

[0010] Next, a method for forming the foregoing two-layer structure willbe described with reference to cross-sectional views of FIGS. 3A to 3C.

[0011] As a method for etching the foregoing upper oxide film andpolysilicon film, a gas containing CF₄ and O₂ is used, and the entireupper oxide film 604 and a part of the polysilicon film 603 aresimultaneously etched by reactive ions. The etching conditions in thiscase are set as:

[0012] Gas mixture ratio: CF₄:O₂=4:1

[0013] RF power: 700 W

[0014] In these etching conditions, the foregoing two-layer structure isetched close to vertically.

[0015] The residual polysilicon film is etched under the followingetching conditions by use of the gas containing CF₄ and O₂:

[0016] Gas mixture ratio: CF₄: O₂=4:1

[0017] RF power: 300 W

[0018] Specifically, the RF power in the above conditions is loweredthan that in the initial etching conditions. In this type of low RFpower condition, an etching rate for the polysilicon film 603 is higherthan that for the lower oxide film 602. Thus, the etching for the loweroxide film is restricted to the minimum. However, in this case, theetching rate for the upper oxide film on the polysilicon film 603 issimultaneously slowed. Hence, at the time when the etching for thepolysilicon film is completed, the polysilicon film is over-etched inthe lateral direction with respect to the upper and lower oxide films,and the upper oxide film 604 is formed into a shape overhanging thepolysilicon film 603.

[0019] In addition, after forming the two-layer structure, its surfaceis cleaned by a diluted hydrofluoric acid treatment for approximately 10seconds, followed by deposition of the gate oxide film. The overhang ofthe oxide film, which is formed by etching the polysilicon film, can beremoved by etching using the diluted hydrofluoric acid treatment becausethe film thickness of the upper oxide film is 10 nm. Because the etchingrate by the diluted hydrofluoric acid treatment is several nm/min, theportion of the oxide film, which hangs during the work of immersion ofthe substrate for 10 seconds and pull-up thereof, is removed by etchingfrom the upper and lower sides thereof. Hence, it is necessary to thinthe film thickness of the two-layer structure to 10 nm (60 nm for thepolysilicon film) If the film thickness of the upper oxide film isthickened more than 10 nm, then the time necessary for the dilutedhydrofluoric acid treatment, required for removing the overhang, must bemore than 10 seconds, and an excessive etching of the lower oxide filmoccurs on an interface between the polysilicon film and the lower oxidefilm. In addition, if the polysilicon film is thickened to more than 60nm, then variations in etching in the case of selectively removing thepolysilicon film by etching are increased, thus making it difficult tocontrol the dimension of the polysilicon film and to switch off the TFT.

[0020] As described above, if the conventional process is used, then theexcessive etching of the lower oxide film has hardly occurred under thepolysilicon film, and the two-layer structure has been formed such thatits side face can be close to vertical.

[0021] As shown in FIG. 2B which is the cross-sectional view obtained bycutting the plan view of FIG. 2A, the conventional two-layer structureis formed into a shape in which the side faces of the upper oxide film504 and polysilicon film 503 are close to vertical with respect to thebase.

[0022] Hence, if the three-layer film formed of the gate oxide film 505,the micro-crystalline silicon film 506 for the gate electrode and the Crfilm 507 is deposited on the two-layer structure, the three-layer filmis thickened on the two-layer structure and the lower oxide filmexcluding the same on the two-layer structure, and thinned on thesidewall portion of the two-layer structure. This means that thethree-layer film does not sufficiently cover the sidewall step portionof the two-layer structure. As a result, a stress concentrates upon thethree-layer film located on the sidewall of the two-layer structure, andthe crack 515 occurs on the three-layer film. If the crack 515 exists onthe three-layer film, then there is a possibility that a short-circuitof the gate electrode will occur in the portion of the crack 515 whenthe impurities contained in the polysilicon film in the two-layerstructure are activated by use of a laser. Particularly, in the case ofcomposing the gate electrode from a high melting point metal of acolumnar structure, such as Cr, as in the present invention, thestructure is weak against stress, and the crack 515 is more prone tooccur.

[0023] In general, the surface of the polysilicon film configuring thetwo-layer structure is uneven, and its morphology is bad. Therefore, itis thought that the gate oxide film and the gate electrode on thetwo-layer structure are not evenly deposited and that the cracks becomeprone to occur on the thin portions of the gate oxide film and gateelectrode.

SUMMARY OF THE INVENTION

[0024] It is an object of the present invention to provide, with regardto a stacked structure of a lower oxide film, a semiconductor film andan upper oxide film, a method for forming a pattern of a stacked filmcomposed of a semiconductor film and an upper oxide film, the pattern ofthe stacked film being capable of absorbing a physical stress on aninsulating film and wiring, which cover the pattern of the stacked film,and capable of preventing a crack of the insulating film and adisconnection.

[0025] The method for forming a pattern of a stacked film according tothe present invention includes the steps of: sequentially depositing afirst oxide film, a semiconductor film and a second oxide film on asubstrate; laser annealing the semiconductor film; forming a resistpattern on the second oxide film; and forming the pattern of the stackedfilm composed of the semiconductor film and the second oxide film by dryetching the second oxide film and the semiconductor film by use of theresist pattern as a mask, wherein fluorine-based gas is used as anetching gas for use in the dry etching in the step of forming a patternof a stacked film.

[0026] The method for forming a pattern of a stacked film according tothe present invention further performs the dry etching while setting agas ratio of CF₄ and O₂ in a mixture gas thereof at 1:1 to make a taperangle of the second oxide film of the pattern of the stacked film largerthan a taper angle of the semiconductor film, and the taper angles ofthe second oxide film and semiconductor film are controlled into rangesof 45°<θ<60° and 10°<γ<60°, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1A is a plan view of a two-layer structure composed of asemiconductor film and a second oxide film;

[0028]FIG. 1B is a cross-sectional view obtained by cutting thetwo-layer structure of FIG. 1A along a line I-I;

[0029]FIG. 2A is a plan view of a two-layer structure;

[0030]FIG. 2B is a cross-sectional view obtained by cutting thetwo-layer structure of FIG. 2A along a line

[0031]FIG. 3A is a cross-sectional view of a two-layer structure,illustrating an initial step of a method for forming a two-layerstructure;

[0032]FIG. 3B is a cross-sectional view illustrating a step followingFIG. 3A;

[0033]FIG. 3C is a cross-sectional view illustrating a step followingFIG. 3B;

[0034]FIG. 4A is a plan view of a thin film transistor;

[0035]FIG. 4B is a cross-sectional view obtained by cutting the planview of FIG. 4A along a line I-I;

[0036]FIG. 5A is a plan view of the thin film transistor;

[0037]FIG. 5B is a cross-sectional view obtained by cutting the planview of FIG. 5A along a line II-II;

[0038]FIG. 6 is a cross-sectional view illustrating a step followingFIG. 5B;

[0039]FIG. 7A is a cross-sectional view of a two-layer structure,illustrating an initial step for explaining a procedure for tapering asemiconductor film and a second oxide film, which configures a two-layerstructure;

[0040]FIG. 7B is a cross-sectional view illustrating a step followingFIG. 7A;

[0041]FIG. 7C is a cross-sectional view illustrating a step followingFIG. 7B;

[0042]FIG. 8 is a graph showing changes of etching rates of etched filmswhen a ratio of CF₄:O₂ is increased from 4:1 to 1:1 or the like inreactive ion etching by a gas containing CF₄ and O₂; and

[0043]FIG. 9 is a graph showing RF power dependencies of etching ratesof etching gases for etched films.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] A manufacturing flow of a thin film transistor device accordingto a first embodiment of the present invention is illustrated in FIGS.4A, 4B, 5A and 5B. FIGS. 4A and 5A are plan views of the thin filmtransistor, and FIGS. 4B and 5B are cross-sectional views obtained bycutting the plan views of FIGS. 4A and 5A along directions I-I andII-II, respectively.

[0045] In FIGS. 4B and 5B, the lower oxide film 102 is deposited in athickness of approximately 300 nm on the glass substrate 101, and thesilicon film 103 and the upper oxide film 104, which configure atwo-layer structure, are deposited in thicknesses of 60 nm and 10 nm,respectively, on the lower oxide film 102. Thereafter, the silicon film103 is crystallized by an excimer laser. The silicon film 103 that hasbeen crystallized by the excimer laser will be described below as thepolysilicon film 103.

[0046] Next, the polysilicon film 103 and the upper oxide film 104,which configure the two-layer structure, are simultaneously dry etched.By this type of simultaneous etching for the two-layer structure, thetapers of the upper oxide film 104 and polysilicon film 103 with respectto the plane of the glass substrate 101 are set in ranges of: 45°<θ<60°;and 10°<γ<60°, respectively.

[0047] Subsequently, as illustrated in FIG. 6, after forming thetwo-layer structure, high-concentration phosphorus ions and phosphorusfor a LDD are doped into the polysilicon film 103, thus forming thesource/drain region 110 and the LDD region 111. Thereafter, the gateoxide film 105 is formed in a thickness of 45 nm to cover the two-layerstructure.

[0048] Furthermore, a two-layer film composed of the micro-crystallinesilicon film 106 and the Cr film 107 is deposited and etched, thusforming a gate electrode. For the gate electrode, the Cr film 107 isused as a high melting point metal that is excellent at resisting heatand low in electric resistance. In addition, the μc-Si film 106 is usedas an interlayer material film between the gate oxide film 105 and theCr film 107 in order to optimize a work function of the gate electrodeand because of the ease with which it controls threshold values. For thehigh melting point metal utilized as the gate electrode material, W, Mo,Ti, Ta or a silicide film of any of these is used as well as Cr.

[0049] Thereafter, the first interlayer oxide film 109 is furtherdeposited in a thickness of 100 nm, followed by a heat treatment at atemperature equal to or more than 350° C. to activate impurities in thephosphorus-doped polysilicon film 103, thus lowering the electricresistance of the polysilicon film.

[0050] Following the steps described above, the second interlayer oxidefilm 112 is further deposited in a thickness of 300 nm. Subsequently,the first and second interlayer oxide films 109 and 112 are opened toform the contact 113 to communicate with the polysilicon film. Then, thealuminum wiring 114 is provided, thus forming a desired thin filmtransistor.

[0051] Next, a method for setting the tapers of the upper oxide film andpolysilicon film of the two-layer structure in the ranges of: 45°<θ<60°;and 10°<γ<60°, respectively, with respect to the planer surface of theglass substrate 201 by the simultaneous etching of the upper oxide filmand the polysilicon film will be described, with reference to FIGS. 7A,7B and 7C.

[0052] First, as illustrated in FIG. 7A, the pattern of the photoresist208 is formed on the upper oxide film 204.

[0053] Subsequently, as illustrated in FIG. 7B, reactive ion etching isconducted on the upper oxide film 204 and the polysilicon film 203 by agas containing CF₄ and O₂, using the photoresist 208 as an etching mask.The gas ratio of CF₄ and O₂ during this etching is set at 1:1, thustapering the side face of the two-layer structure of the upper oxidefilm/polysilicon film in the range of 45°<θ<60°. Note that, beside thegas containing CF₄ and O₂, a mixed gas containing a fluorine-based gas,such as CHF₃ and SF₆, and O₂ is used.

[0054] Next, as illustrated in FIG. 7C, the etching gas is switched to agas containing Cl₂ and O₂ at the time when the polysilicon film isetched and the lower oxide film is exposed. The etching rate of the gascontaining Cl₂ and O₂ for the polysilicon film is higher than that forthe oxide film, thus making it possible to restrict the etching of thelower oxide film 202 to the minimum. In addition, by setting the gasratio of Cl₂ and O₂ at 1:1, the side face of the polysilicon film 203 inthe vicinity of the interface with the lower oxide film 202 can befurther slanted. In this case, the deposition reaction product 214 iscreated on the sidewall of the resist 208 and the sidewall of thetwo-layer structure of the upper oxide film/polysilicon film. Therefore,the side etching of the polysilicon film 203 is prevented. Hence, thetaper of the two-layer structure of the upper oxide film/polysiliconfilm, which is formed by use of the gas containing the CF₄ and O₂ in thegas ratio of 1:1, can be maintained. Simultaneously, the polysiliconfilm 203 remaining on the lower oxide film 202 due to etching variationsin the glass substrate 201 is removed by the gas containing Cl₂ and O₂.Particularly, the taper angle of the polysilicon film 203 on theinterface with the lower oxide film 202 ranges as: 10°<γ<60° due to theetching variations in the glass substrate.

[0055] As described above, if the method for manufacturing a thin filmtransistor in accordance with the first embodiment of the presentinvention is used, the taper angle of the side face of the two-layerstructure can be reduced to 45°. Hence, as illustrated in FIG. 5B, whichis a cross-sectional view obtained by cutting, along the line II-II, theportion of the two-layer structure illustrated in the plan view of FIG.5A, the three-layer film composed of the gate oxide film 105, the μc-Sifilm 106 and the Cr film 107, which is deposited on the two-layerstructure, is thickened on the sidewall step portion of the two-layerstructure. Hence, the concentration of the stress on the oxide film 105and the gate electrode (μc-Si film 106 and Cr film 107) in the sidewallportion of the two-layer structure is absorbed, and thus thedisconnection of the gate electrode does not occur even if the thin filmtransistor is subjected to a heat treatment in a later step.

[0056] Next, a method for controlling the taper angles of the upperoxide film/polysilicon film using simultaneous etching in the method formanufacturing a thin film transistor device in accordance with the firstembodiment of the present invention will be described below.

[0057]FIG. 8 shows changes of the etching rates of the oxide film,polysilicon film and resist when the ratio of CF₄:O₂ is increased from4:1 to 1:1 or the like in the reactive ion etching by the gas containingCF₄ and O₂.

[0058] The etching conditions are: total gas flow amount 200 sccm; gaspressure 20 pa; and RF power 300 W.

[0059] When the flow amount ratio of CF₄ and O₂ contained in the gas foruse in etching is 4:1, the etching rate of the oxide film isapproximately 17 nm/min, and the etching rate of the polysilicon film isapproximately 50 nm/min. The etching rate of the polysilicon film isapproximately three times that of the oxide film. For this, when theratio of O₂ is increased, the etching rate of the oxide film is slightlyincreased while the etching rate of the polysilicon film is decreased.Specifically, when the gas ratio of CF₄: O₂ is 1:1, the etching rate ofthe oxide film becomes approximately 22 nm/min, and the etching rate ofthe polysilicon film becomes approximately 25 nm/min, both of whichbecome approximately equal with each other. As a result of this etchingoperation, the upper oxide film stops protruding with respect to thepolysilicon film, and the side face of the two-layer structure becomessmooth along the interface between the upper oxide film and thepolysilicon film.

[0060] When the gas ratio CF₄:O₂ is 4:1, the etching rate of the resistis 75 nm/min. When the ratio of O₂ is increased, the etching rate of theresist is increased. When the ratio of CF₄ and O₂ is 1:1, the etchingrate of the resist becomes 140 nm/min, which is approximately twice thatin the case of the gas ratio of 4:1. Thus, the etching of the side faceof the resist advances because the etching rate of the resist isincreased as compared with those of the oxide film and polysilicon film.Thus, the etched surface of the resist is set back with respect to theother etched films. The reason that the etching rate of the resist isincreased following the increase of the ratio of the O₂ gas is asfollows.

[0061] Specifically, the composition of the resist is a chemicalcomposition in which CH₂, CH₃ and OH groups are bonded to a benzene ringof phenol novolak resin. In this composition, oxygen radicals in O₂plasma attack the CH₂ and CH₃ groups to dissociate bonds thereof. Thus,the etching rate of the resist film is increased. By the etchingoperation described above, the oxide film and the polysilicon film areuniformly etched while the resist film is being set back in the lateraldirection. In such a way, the side face of the two-layer structure ofthe upper oxide film/polysilicon film can be formed into the gentletaper shape in which the taper angle ranges as: 45°<θ<60° with respectto the plane of the glass substrate.

[0062] Although the example of using the gas containing CF₄ and O₂ hasbeen described in this embodiment, a fluorine-based gas such as CHF₃ andSF₆ may be used in place of CF₄. Also in this case, when the flow amountratio of O₂ is increased in a similar way to that of this embodiment,the etching rate of the polysilicon film is decreased, the etching rateof the oxide film is increased. However, the relationship between theratio of the O₂ content and the taper angle of the side face of thetwo-layer structure differs depending on the type of the fluorine-basedgases.

[0063] Next, the etching operation in the event of switching the etchinggas from the gas containing CF₄ and O₂ to the gas containing Cl₂ and O₂will be described.

[0064] The etching conditions are:

[0065] Total gas flow amount: 400 sccm;

[0066] Gas flow amount ratio: Cl₂:O₂=1:1;

[0067] Gas pressure: 40 pa; and

[0068] RF power: 400 W

[0069] In the etching by the gas containing Cl₂ and O₂, the etching rateratio of the polysilicon film to the oxide film is as large asapproximately 10, and therefore, the etching of the lower oxide film canbe restricted to the minimum. In addition, in the etching by the gascontaining Cl₂ and O₂ in the flow amount ratio of 1: 1, the resist onthe polysilicon film is set back in a similar way to that of the etchingby the gas containing CF₄ and O₂ in the flow amount ratio of 1:1, andthe side face of the polysilicon film is tapered with a low angle.Simultaneously, SiCl_(x)O_(y) that is a reaction product of the etchingis deposited, thus facilitating the formation of the sidewall on thetwo-layer structure of the upper oxide film/polysilicon film. Hence, theside face of the polysilicon film is tapered, and the side etching ofthe two-layer structure of the upper oxide film/polysilicon film isprevented. Moreover, the etching amount of the lower oxide film can berestricted to the minimum while maintaining the taper added to the sideface of the two-Layer structure of the upper oxide film/polysiliconfilm.

[0070] Timing when the polysilicon film is etched and the lower oxidefilm is exposed in the foregoing operation will be described below. Thepolysilicon film is etched fast in an outer region of the glasssubstrate because the etching advances fast there. Hence, at the pointof time when the lower oxide film in this region is exposed, the etchingof the polysilicon film is not yet completed in an inner region of theglass substrate, where the etching advances slowly. If the etching gasis switched to the gas containing Cl₂ and O₂ at this point of time,then, in the polysilicon film in the region where the etching advancesslowly as described above, the resist is continuously set back in asimilar way to the previous etching by the gas containing CF₄ and O₂.Simultaneously, the etching product is deposited on the side face of thetwo-layer structure of the already etched upper oxide film/polysiliconfilm. Specifically, in the region where the etching of the polysiliconfilm advances in the film-thickness direction, etching by theaccelerated ion components of the etching gas is conducted. In addition,the etching product is deposited on the etched side face of thepolysilicon film in the region where the polysilicon film is alreadyetched in the film-thickness direction, and the side etching by theradical components of the etching gas is prevented. Moreover, in theetching by the gas containing Cl₂ and O₂, it is thought that the taperangle set in the range of 45°<θ<60° on the side face of the polysiliconfilm formed under the previous etching conditions by CF₄ and O₂ isfurther reduced by the etching product deposited on the side face of thepolysilicon film. The reason is as follows. In the etching by the gascontaining Cl₂ and O₂, the etching product is uniformly deposited onalmost the entire surface, and simultaneously, the deposition on thesurface to be etched is etched by the incidence of the reactive ions.Then, when the object to be etched is exposed, the etching advances.However, the vertically incident ions cannot remove the depositionentirely because the resist and the etching product of the sidewallportion of the two-layer structure of the upper oxide film/polysiliconfilm are thick, and the etching product remains on the sidewall. Hence,the width of the two-layer structure is expanded as the etching advancesin the film thickness direction due to the existence of the etchingproduct. In such a way, the etching product is deposited on the sideface of the polysilicon film, and the width of the two-layer structureis expanded from the bottom as the etching advances, thus forming thetaper.

[0071] As described above, it is thought that, in the side face of thetwo-layer structure tapered in the angle ranging as: 45°<θ<60°, thetaper angle is further reduced by use of the gas in which the flowamount ratio of Cl₂ and O₂ is 1:1. Hence, in the outer region of thesubstrate, where the etching advances fast, the taper in the range of:45°<θ<60°, which is formed under the previous etching conditions of CF₄and O₂, is maintained by the deposition of the etching product on thesidewall. In the inner region of the substrate, where the etchingadvances slowly, the polysilicon film on the interface portion betweenthe polysilicon film and the lower oxide film, that is, the polysiliconfilm etched by the gas containing Cl₂ and O₂, reduces its taper anglemore than the taper angle in the range of: 45°<θ<60°, which is formed bythe previous etching by the gas containing CF₄ and O₂. The taper angleof the polysilicon film in the concerned portion is reduced toapproximately 10°. Hence, the taper angle of the polysilicon filmbecomes an angle ranging as 10°<γ<60° in the entire substrate due to thedistributions as to how the etching advances in the glass substrate.

[0072] Next, as to how the pattern precision of the two-layer structureof the upper oxide film/polysilicon film is changed in the case oftapering the same by the reactive ion etching will be described below.

[0073] The etching rate for the resist under the reactive ion etchingconditions in which the gas ratio of CF₄ and O₂ is 1:1 indicates theetching rate of the etching in the vertical direction. It is assumedthat the etching rate in the lateral direction is approximately twothirds that in the vertical direction, and that the two-layer structureof the upper oxide film/polysilicon film is entirely etched under theetching conditions where the gas ratio of CF₄ and O₂ is 1:1. The setbackamount of the resist in the lateral direction in this case is estimatedto be approximately 0.27 μm based on the calculation of the etchingrates for the respective films. Hence, the deviation, from a designvalue, of the value in the case of vertically etching the two-layerstructure of the upper oxide film/polysilicon film is 0.27 μm.

[0074] Next, assuming that the taper angle of the side face of thetwo-layer structure when etching the two-layer structure of the upperoxide film/polysilicon film is 60°, then the deviation of the value inthis case from the design value is estimated to be approximately 0.23μm.

[0075] Hence, the two-layer structure of the upper oxidefilm/polysilicon film is formed into the taper shape of 60° or less bythe reactive ion etching, thus making it possible to control thedeviation from the design value within 0.23 μm.

[0076] Although the gas flow amount ratio of CF₄ and O₂ in the presentinvention is set at 1:1, the taper angle of the two-layer structure canbe further reduced if the gas flow amount ratio of O₂ is furtherincreased. However in this case, the etching rate for the polysilicon isreduced to greatly increase the etching time. Thus, the dimensionalprecision of the two-layer structure is deteriorated. Hence, 1:1 isthought to be reasonable for the gas flow amount ratio of CF₄ and O₂.

[0077] With regard to the film thicknesses of the films of the two-layerstructure, it is desirable to set the thickness of the upper oxide filmequal to 10 nm and the thickness of the polysilicon film equal to 60 nm.This is because the variations due to the etching are increased in thecase of etching the upper oxide film and the polysilicon film whenthickening the upper oxide film more than 10 nm and the polysilicon filmmore than 60 nm. The two-layer structure formed in this state isdeteriorated in dimensional precision, leading to the deterioration ofthe OFF characteristics of the TFT.

[0078] As mentioned above, in accordance with the contents of thepresent invention, in the two-layer film of the two-layer structureportion, the taper angle of the upper oxide film of the island portionis controlled in the range of: 45°<θ<60°, and the taper angle of thepolysilicon layer thereof is controlled in the range of 10°<γ<60°. Thus,the step coverage for the gate oxide film and the Cr/μc-Si stacked filmafter the formation of the two-layer structure is enhanced. Moreover,the disconnection of the gate electrode can be prevented in a portionwhere the gate electrode crosses over the two-layer structure. Inaddition, the lower oxide film of the two-layer structure is made not tobe etched as much as possible, thus reducing the excessive etching andside etching of the lower oxide film of the two-layer structure. Thus,the coverage defect of the gate oxide film and the disconnection of thegate electrode can be prevented.

[0079] Meanwhile, the two-layer structure of the lower oxidefilm/polysilicon film in the present invention is tapered, thus makingit possible to prevent the occurrence of the crack in the gate electrodewhich crosses over the two-layer structure.

[0080] Next, a second embodiment of the method for forming a pattern ofa stacked film of the present invention will be described. In the secondembodiment, the etching time for the reactive ion etching by the gascontaining CF₄ and O₂ when forming the two-layer structure of the loweroxide film/polysilicon film is shortened. FIG. 9 shows RF powerdependencies of etching rates, for respective films, of etching gasesfor use in the second embodiment.

[0081] Similarly to the first embodiment, the upper oxide film and thepolysilicon film undergo the reactive ion etching by the gas series ofCF₄ and O₂ by use of the photoresist as an etching mask until the loweroxide film is exposed. In this case, in the second embodiment, theetching conditions are set as:

[0082] gas flow amount ratio of CF₄ and O₂:1:1;

[0083] total gas flow amount: 200 sccm;

[0084] gas pressure: 20 Pa; and

[0085] RF power: 300 W and 500 W

[0086] When the RF power is increased from 300 W to 500 W, though theetching rate for the polysilicon film is approximately doubled (40nm/min), its selective etching ratio comparing with the lower oxide filmis hardly changed (=approximately 1), and its selective etching ratiocomparing with the photoresist is hardly changed (=approximately 6),either. Therefore, the etching time can be shortened while maintainingthe taper angle of the upper oxide film of the two-layer structure inthe range of: 45°<θ<60° and the taper angle of the polysilicon layerthereof in the rage of: 10°<γ<60°, thus making it possible to enhancethe processing capability of the apparatus. Moreover, when the etchingrate is increased, a ratio of a change in intensity of plasma emissionfor use in detecting the end point of the etching is increased, andtherefore, a definite detection for the end point can be performed.

[0087] From the point of time when the lower oxide film is exposed, theetching gas is switched to the gas containing Cl₂ and O₂. Thus, theetching amount of the lower oxide film can be minimized, and the sideetching of the polysilicon film can also be restricted. Accordingly, thetaper of the two-layer structure processed by the gas series of CF₄ andO₂ can be maintained. Hence, the step coverage of the gate insulatingfilm and gate electrode, which cross over the two-layer structure afterthe formation thereof is enhanced, thus making it possible to preventthe gate electrode from being disconnected.

[0088] As described above, according to the method for forming a patternof a stacked film, the first oxide film, the semiconductor film and thesecond oxide film are sequentially deposited on the substrate, and thesemiconductor film is laser annealed. Thereafter, the resist pattern isformed on the second oxide film, and by use of the resist pattern as amask, the second oxide film and the semiconductor film are dry etched toform the pattern of the stacked film (two-layer structure) composed ofthe semiconductor film and the second oxide film. At this time, thefluorine-based gas is used as the dry etching gas for the second oxidefilm and the semiconductor film, and the etching gas is switched fromthe fluorine-based gas to the chlorine-based gas at the point of timewhen the first oxide film is exposed. The mixed gas of CF₄ and O₂ isused as the fluorine-based gas, and suitably, the gas ratio of CF₄ andO₂ in the mixed gas is set at 1:1, thus conducting the dry etchingtherefor. In such a way, the taper angle of the second oxide film of thepattern of the stacked film can be made larger than the taper angle ofthe semiconductor film thereof. Specifically, the taper angles of thesecond oxide film and semiconductor film can be controlled into theranges of: 45°<θ<60° and 10°<γ<60°, respectively. Hence, the stepdisconnection of the wiring that crosses over this pattern of thestacked film can be prevented.

1-7. (Canceled)
 8. A stacked film for a thin film transistor, saidstacked film comprising: a first oxide film formed on a substrate; apolysilicon film formed on said first oxide film and having a taperangle in a range 10°<γ<60°; and a second oxide film formed on saidpolysilicon film and having a taper angle in a range 45°<θ<60°.